I am currently working as an R&D engineer and serving as the Deputy Director of UCLA CHIPS, where I oversee daily operations, mentor PhD and master's students, and actively seek funding to support research initiatives. My independent research here focuses on Advanced Packaging and 3DHI, specifically in optimizing direct Cu-Cu TCB for fine bump-pitch (< 10mm), multi-tier 3D stacking of chiplets for HPC applications. I am also developing a novel backside power delivery technology for Si-IF using integrated micro-transformers. Prior to this, I served as a Senior Project Associate at CPPICS Lab, IIT-Madras, where I led experimental research on Optical & RF packaging for Si-PICs. I am skilled in Ansys HFSS, Keysight ADS, Cadence APD, SOLIDWORKS, and Ansys Lumerical & Python. Earlier in my career, I worked as a graduate researcher in UCLA CHIPS on GaN microLED mass transfer and FOWLP for developing flexible microLED displays, resulting in two patents. My areas of interest are Advanced Packaging, Heterogeneous Integration, Optical/RF Packaging, & Micro-fabrication.